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1 ltc3704 3704fb features descriptio u applicatio s u typical applicatio u wide input range, no r sense tm positive-to-negative dc/dc controller the ltc ? 3704 is a wide input range, current mode, positive-to-negative dc/dc controller that drives an n-channel power mosfet and requires very few external components. intended for low to high power applications, it eliminates the need for a current sense resistor by utilizing the power mosfets on-resistance, thereby maxi- mizing efficiency. the ics operating frequency can be set with an external resistor over a 50khz to 1mhz range, and can be synchro- nized to an external clock using the mode/sync pin. burst mode operation at light loads, a low minimum operating supply voltage of 2.5v and a low shutdown quiescent current of 10 a make the ltc3704 ideally suited for battery-operated systems. for applications requiring constant frequency operation, the burst mode operation feature can be defeated using the mode/sync pin. higher than 36v switch voltage applications are possible with the ltc3704 by connecting the sense pin to a resistor in the source of the power mosfet. the ltc3704 is available in the 10-lead msop package. high efficiency operation (no sense resistor required) wide input voltage range: 2.5v to 36v current mode control provides excellent transient response high maximum duty cycle (typ 92%) 1% internal voltage reference 2% run pin threshold with 100mv hysteresis micropower shutdown: i q = 10 a programmable switching frequency (50khz to 1mhz) with one external resistor synchronizable to an external clock up to 1.3 f osc user-controlled pulse skip or burst mode ? operation internal 5.2v low dropout voltage regulator capable of operating with a sense resistor for high output voltage applications (v ds >36v) small 10-lead msop package slic power supplies telecom power supplies portable electronic equipment cable and dsl modems router supplies run i th nfb freq mode/sync sense v in intv cc gate gnd ltc3704 r t 80.6k 1% r1 1m c vcc 4.7 f m1 c in , c dc : tdk c5750x5r1c476m c out : tdk c5750x5r0j107m c vcc : taiyo yuden lmk316bj475ml d1 ? l1* l2* c out 100 f (x2) v in 5v to 15v v out C5.0v 3a to 5a gnd d1: mbrd835l (on semiconductor) l1, l2: bh electronics bh510-1009 m1: si4884 (siliconix/vishay) r c 3k c c1 4.7nf c in 47 f c dc 47 f 3704 ta01 ? r fb1 1.21k 1% r fb2 3.65k 1% conversion efficiency output current (a) 0.001 efficiency (%) 0.1 10 100 90 80 70 60 50 40 30 20 3704 ta01b 0.01 1.0 v in = 15v v in = 5v v in = 10v figure 1. high efficiency positive to negative supply , ltc, lt and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. no r sense is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5847554, 5731694.
2 ltc3704 3704fb (note 1) v in voltage ............................................... e 0.3v to 36v intv cc voltage ........................................... e 0.3v to 7v intv cc output current ........................................ 50ma gate voltage ........................... e 0.3v to v intvcc + 0.3v i th voltage ............................................... e 0.3v to 2.7v nfb voltage .............................................. e2.7v to 2.7v run, mode/sync voltages ....................... e 0.3v to 7v freq voltage ............................................e 0.3v to 1.5v sense pin voltage ................................... e 0.3v to 36v operating temperature range (note 2) .. e 40 c to 85 c ltc3704e ............................................ e40 c to 85 c ltc3704i ........................................... e40 c to 125 c junction temperature (note 3) ............................ 125 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc3704ems ltc3704ims absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics ms part marking ltyt ltcfw consult ltc marketing for parts specified with wider operating temperature ranges. the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v intvcc = 5v, v run = 1.5v, r t = 80k, v mode/sync = 0v, unless otherwise specified. symbol parameter conditions min typ max units main control loop v in(min) minimum input voltage 2.5 v i q input voltage supply current (v intvcc = open, no switching) (note 4) continuous mode v mode/sync = 5v, v ith = 0.75v 550 1000 r a burst mode operation, no load v mode/sync = 0v, v ith = 0v (note 5) 250 500 r a shutdown mode v run = 0v 10 20 r a v run + rising run input threshold voltage v intvcc = open 1.348 v v run e falling run input threshold voltage v intvcc = open 1.223 1.248 1.273 v 1.198 1.298 v v run(hyst) run pin input threshold hysteresis 50 100 150 mv i run run input current 1 100 na v nfb negative feedback voltage v ith = 0.4v (note 5) e1.218 e1.230 e1.242 v v ith = 0.4v (note 5) e1.212 e1.248 v v ith = 0.4v (i-grade) (notes 2 and 5) e1.205 e1.255 v i nfb nfb pin input current 7.5 15 r a ) v nfb line regulation 2.5v f v in f 30v 0.002 0.02 %/v ) v in ) v nfb load regulation v mode/sync = 0v, v ith = 0.5v to 0.90v (note 5) e1 e0.1 % ) v ith g m error amplifier transconductance i th pin load = 5 r a (note 5) 650 r mho v ith(burst) burst mode operation i th pin voltage falling i th voltage 0.17 v v sense(max) maximum current sense input threshold duty cycle < 20% 120 150 180 mv i sense(on) sense pin current (gate high) v sense = 0v 40 75 r a i sense(off) sense pin current (gate low) v sense = 30v 0.1 5 r a order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ t jmax = 125 c, v ja = 120 c/ w 1 2 3 4 5 run i th nfb freq mode/ sync 10 9 8 7 6 sense v in intv cc gate gnd top view ms package 10-lead plastic msop
3 ltc3704 3704fb electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliabilty and lifetime. note 2: the ltc3704e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3704i is guaranteed over the full C40 c to 125 c operating temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 120 c/w) note 4: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see applications information. note 5: the ltc3704 is tested in a feedback loop that servos v nfb to the reference voltage with the i th pin forced to a voltage between 0v and 1.4v (the no load to full load operating voltage range for the i th pin is 0.3v to 1.23v). note 6: in a synchronized application, the internal slope compensation gain is increased by 25%. synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. note 7: rise and fall times are measured at 10% and 90% levels. the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v intvcc = 5v, v run = 1.5v, r freq = 80k, v mode/sync = 0v, unless otherwise specified. symbol parameter conditions min typ max units oscillator f osc oscillator frequency r freq = 80k 250 300 350 khz oscillator frequency range 50 1000 khz d max maximum duty cycle 87 92 97 % f sync/ f osc recommended maximum synchronized f osc = 300khz (note 6) 1.25 1.30 frequency ratio t sync(min) mode/sync minimum input pulse width v sync = 0v to 5v 25 ns t sync(max) mode/sync maximum input pulse width v sync = 0v to 5v 0.8/f osc ns v il(mode) low level mode/sync input voltage 0.3 v v ih(mode) high level mode/sync input voltage 1.2 v r mode/sync mode/sync input pull-down resistance 50 k v freq nominal freq pin voltage 0.62 v low dropout regulator v intvcc intv cc regulator output voltage v in = 7.5v 5.0 5.2 5.4 v v intvcc intv cc regulator line regulation 7.5v v in 15v 8 25 mv v in1 v intvcc intv cc regulator line regulation 15v v in 30v 70 200 mv v in2 v ldo(load) intv cc load regulation v in = 7.5v, 0 i intvcc 20ma C 2 C 0.2 % v dropout intv cc regulator dropout voltage v intvcc = open, intv cc load = 20ma 280 mv i intvcc bootstrap mode intv cc supply run = 0v, sense = 5v 10 20 a current in shutdown gate driver t r gate driver output rise time c l = 3300pf (note 7) 17 100 ns t f gate driver output fall time c l = 3300pf (note 7) 8 100 ns
4 ltc3704 3704fb nfb voltage vs temp nfb voltage line regulation nfb pin current vs temperature temperature ( c) C50 nfb voltage (v) C1.23 C1.24 150 3704 g01 C1.22 C1.21 0 50 100 C25 25 75 125 C1.25 v in (v) 0 C1.229 nfb voltage (v) C1.230 C1.231 5101520 3704 g02 25 30 35 shutdown mode i q vs v in burst mode i q vs v in v in (v) 0 0 shutdown mode i q ( a) 10 20 10 20 30 40 3704 g04 30 shutdown mode i q vs temperature temperature ( c) C50 0 shutdown mode i q ( a) 5 10 15 20 C25 0 25 50 3704 g05 75 100 125 150 v in = 5v v in (v) 0 0 burst mode i q ( a) 100 200 300 400 600 10 20 3704 g06 30 40 500 burst mode i q vs temperature gate drive rise and fall time vs c l dynamic i q vs frequency temperature ( c) C50 0 burst mode i q ( a) 200 500 0 50 75 3704 g07 100 400 300 C25 25 100 125 150 frequency (khz) 0 0 i q (ma) 2 6 8 10 800 18 3704 g08 4 400 1200 600 200 1000 12 14 16 c l = 3300pf i q(tot) = 550 a + qg ? f c l (pf) 0 0 time (ns) 10 20 30 40 60 2000 4000 6000 8000 3704 g09 10000 12000 50 rise time fall time typical perfor a ce characteristics uw temperature ( c) C50 nfb current ( a) 8.0 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 C25 25 0 50 100 75 3704 g03 125 150
5 ltc3704 3704fb run thresholds vs v in r t vs frequency frequency vs temperature sense pin current vs temperature maximum sense threshold vs temperature intv cc load regulation intv cc dropout voltage vs current, temperature intv cc line regulation v in (v) 0 1.2 run thresholds (v) 1.3 1.4 10 20 30 40 3704 g10 1.5 run thresholds vs temperature temperature ( c) C50 run thresholds (v) 1.30 1.35 150 3704 g11 1.25 1.20 0 50 100 C25 25 75 125 1.40 frequency (khz) 100 r t (k ) 300 1000 3704 g12 10 100 200 1000 900 800 700 600 500 400 0 temperature ( c) C50 275 gate frequency (khz) 280 290 295 300 325 310 0 50 75 3704 g13 285 315 320 305 C25 25 100 125 150 temperature ( c) C50 140 max sense threshold (mv) 145 150 155 160 C25 0 25 50 3704 g14 75 100 125 150 temperature ( c) C50 35 sense pin current ( a) 40 45 0 50 75 3704 g15 C25 25 100 125 150 gate high v sense = 0v intv cc load (ma) 0 intv cc voltage (v) 5.2 30 50 80 3704 g16 5.1 5.0 10 20 40 60 70 t a = 25 c v in (v) 0 5.1 intv cc voltage (v) 5.2 5.3 10 20 30 40 3704 g17 5.4 515 25 35 t a = 25 c intv cc load (ma) 0 0 dropout voltage (mv) 50 150 200 250 500 350 5 10 3704 g18 100 400 450 300 15 20 150 c 75 c 125 c 25 c C50 c 0 c typical perfor a ce characteristics uw
6 ltc3704 3704fb uu u pi fu ctio s run (pin 1): the run pin provides the user with an accurate means for sensing the input voltage and pro- gramming the start-up threshold for the converter. the falling run pin threshold is nominally 1.248v and the comparator has 100mv of hysteresis for noise immunity. when the run pin is below this input threshold, the ic is shut down and the v in supply current is kept to a low value (typ 10 a). the absolute maximum rating for the voltage on this pin is 7v. i th (pin 2): error amplifier compensation pin. the cur- rent comparator input threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.40v. nfb (pin 3): receives the feedback voltage from the external resistor divider across the output. nominal voltage for this pin in regulation is C1.230v. freq (pin 4): a resistor from the freq pin to ground programs the operating frequency of the chip. the nomi- nal voltage at the freq pin is 0.62v. mode/sync (pin 5): this input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. if the mode/ sync pin is connected to ground, burst mode operation is enabled. if the mode/sync pin is connected to intv cc , or if an external logic-level synchronization signal is applied to this input, burst mode operation is disabled and the ic operates in a continuous mode. gnd (pin 6): ground pin. gate (pin 7): gate driver output. i ntv cc (pin 8): the internal 5.20v regulator output. the gate driver and control circuits are powered from this voltage. decouple this pin locally to the ic ground with a minimum of 4.7 f low esr tantalum or ceramic capacitor. v in (pin 9): main supply pin. must be closely decoupled to ground. sense (pin 10): the current sense input for the control loop. connect this pin to the drain of the power mosfet for v ds sensing and highest efficiency. alternatively, the sense pin may be connected to a resistor in the source of the power mosfet. internal leading edge blanking is provided for both sensing methods.
7 ltc3704 3704fb block diagra w C + C + 50k ea uv to start-up control burst comparator s r q logic pwm latch current comparator 0.30v 1.230v 5.2v C + 2.00v 1.230v slope 1.230v i loop nfb i th C + g m 3 mode/sync 5 freq 4 2 intv cc 8 ldo v-to-i osc v-to-i slope compensation bias and start-up control v in bias v ref i osc r loop C + C + c1 sense 10 gnd 3704 bd 6 gate intv cc gnd 7 v in 1.248v 9 run 1 0.62v 100mv hysteresis (1.348v rising) buffer 200k 200k c2
8 ltc3704 3704fb main control loop the ltc3704 is a constant frequency, current mode controller for dc/dc positive-to-negative converter appli- cations. the ltc3704 is distinguished from conventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power mosfet switch instead of across a discrete sense resistor, as shown in figure 2. this sensing technique improves efficiency, increases power density, and re- duces the cost of the overall solution. operatio u the nominal operating frequency of the ltc3704 is pro- grammed using a resistor from the freq pin to ground and can be controlled over a 50khz to 1000khz range. in addition, the internal oscillator can be synchronized to an external clock applied to the mode/sync pin and can be locked to a frequency between 100% and 130% of its nominal value. when the mode/sync pin is left open, it is pulled low by an internal 50k resistor and burst mode operation is enabled. if this pin is taken above 2v or an external clock is applied, burst mode operation is disabled and the ic operates in continuous mode. with no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. the run pin controls whether the ic is enabled or is in a low current shutdown state. a micropower 1.248v refer- ence and comparator c2 allow the user to program the supply voltage at which the ic turns on and off (compara- tor c2 has 100mv of hysteresis for noise immunity). with the run pin below 1.248v, the chip is off and the input supply current is typically only 10 a. the ltc3704 can be used either by sensing the voltage drop across the power mosfet or by connecting the sense pin to a conventional shunt resistor in the source of the power mosfet, as shown in figure 2. sensing the voltage across the power mosfet maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36v). by connecting the sense pin to a resistor in the source of the power mosfet, the user is able to program output voltages significantly greater than the 36v maxi- mum input voltage rating for the ic. programming the operating mode for applications where maximizing the efficiency at very light loads (e.g., <100 a) is a high priority, burst mode operation should be applied (i.e., the mode/sync pin should be connected to ground). in applications where fixed frequency operation is more critical than low cur- rent efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the mode/sync pin should be connected to the intv cc pin. this allows discontinuous conduction mode (dcm) operation down to near the limit defined by the chips 2a. sense pin connection for maximum efficiency (v sw < 36v) v sw v in gnd r sense 3704 f02 2b. sense pin connection for precise control of peak i in /i out or for v sw > 36v v sw v in gnd gate gnd v in sense gate gnd v in sense figure 2. using the sense pin on the ltc3704 for circuit operation, please refer to the block diagram of the ic and figure 1. in normal operation, the power mosfet is turned on when the oscillator sets the pwm latch and is turned off when the current comparator c1 resets the latch. the divided-down output voltage is com- pared to an internal 1.230v reference by the error amplifier ea, which outputs an error signal at the i th pin. the voltage on the i th pin sets the current comparator c1 input threshold. when the load current increases, a fall in the nfb voltage relative to the reference voltage causes the i th pin to rise, which causes the current comparator c1 to trip at a higher peak inductor current value. the average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation.
9 ltc3704 3704fb operatio u minimum on-time (about 175ns). below this output current level, the converter will begin to skip cycles in order to maintain output regulation. figures 3 and 4 show the light load switching waveforms for burst mode and pulse-skip mode operation for the converter in figure 1. burst mode operation burst mode operation is selected by leaving the mode/ sync pin unconnected or by connecting it to ground. in normal operation, the range on the i th pin corresponding to no load to full load is 0.30v to 1.2v. in burst mode operation, if the error amplifier ea drives the i th voltage below 0.525v, the buffered i th input to the current com- parator c1 will be clamped at 0.525v (which corresponds to 25% of maximum load current). the inductor current peak is then held at approximately 30mv divided by the power mosfet r ds(on) . if the i th pin drops below 0.30v, the burst mode comparator b1 will turn off the power mosfet and scale back the quiescent current of the ic to 250 a (sleep mode). in this condition, the load current will be supplied by the output capacitor until the i th voltage rises above the 50mv hysteresis of the burst comparator. at light loads, short bursts of switching (where the aver- age inductor current is 25% of its maximum value) fol- lowed by long periods of sleep will be observed, thereby greatly improving converter efficiency. oscilloscope wave- forms illustrating burst mode operation are shown in figure 3. buffered i th burst clamp is removed, allowing the i th pin to directly control the current comparator from no load to full load. with no load, the i th pin is driven below 0.30v, the power mosfet is turned off and sleep mode is invoked. oscilloscope waveforms illustrating this mode of operation are shown in figure 4. 10 s/div 3704 f03 figure 3. ltc3704 burst mode operation (mode/sync = 0v) at low output current figure 4. ltc3704 low output current operation with burst mode operation disabled (mode/sync = intv cc ) v out 50mv/div i l 5a/div mode/sync = 0v (burst mode operation) v out 50mv/div i l 5a/div mode/sync = intv cc (pulse-skip mode) 2 s/div 3704 f04 when an external clock signal drives the mode/sync pin at a rate faster than the chips internal oscillator, the oscillator will synchronize to it. in this synchronized mode, burst mode operation is disabled. the constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. when the oscillators internal logic circuitry detects a synchronizing signal on the mode/sync pin, the internal oscillator ramp is terminated early and the slope compen- sation is increased by approximately 30%. as a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the ic be pro- grammed to be about 75% of the external clock frequency. attempting to synchronize to too high an external fre- quency (above 1.3f o ) can result in inadequate slope com- pensation and possible subharmonic oscillation (or jitter). the external clock signal must exceed 2v for at least 25ns, and should have a maximum duty cycle of 80%, as shown in figure 5. the mosfet turn on will synchronize to the rising edge of the external clock signal. pulse-skip mode operation with the mode/sync pin tied to a dc voltage above 1.2v, burst mode operation is disabled. the internal, 0.525v
10 ltc3704 3704fb applicatio s i for atio wu uu intv cc regulator bypassing and operation an internal, p-channel low dropout voltage regulator pro- duces the 5.2v supply which powers the gate driver and logic circuitry within the ltc3704, as shown in figure 7. the intv cc regulator can supply up to 50ma and must be bypassed to ground immediately adjacent to the ic pins with a minimum of 4.7 f tantalum or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. figure 6. timing resistor (r t ) value figure 5. mode/sync clock input and switching waveforms for synchronized operation 3404 f05 2v to 7v mode/ sync gate i sw t min = 25ns 0.8t d = 40% t t = 1/f o programming the operating frequency the choice of operating frequency and inductor value is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet and diode switching losses. however, lower frequency operation requires more inductance for a given amount of load current. the ltc3704 uses a constant frequency architecture that can be programmed over a 50khz to 1000khz range with a single external resistor from the freq pin to ground, as shown in figure 1. the nominal voltage on the freq pin is 0.6v, and the current that flows into the freq pin is used to charge and discharge an internal oscillator capacitor. a graph for selecting the value of r t for a given operating frequency is shown in figure 6. frequency (khz) 100 r t (k ) 300 1000 3704 f06 10 100 200 1000 900 800 700 600 500 400 0 figure 7. bypassing the ldo regulator and gate driver supply + C + 1.230v r2 r1 p-ch 5.2v driver gate c vcc 4.7 f c in input supply 2.5v to 30v gnd place as close as possible to device pins m1 3704 f07 intv cc v in gnd logic for input voltages that dont exceed 7v (the absolute maximum rating for this pin), the internal low dropout regulator in the ltc3704 is redundant and the intv cc pin can be shorted directly to the v in pin. with the intv cc pin shorted to v in , however, the divider that programs the regulated intv cc voltage will draw 10 a of current from the input supply, even in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . regardless of whether the intv cc pin is shorted to v in or not, it is always necessary to have the driver circuitry bypassed with a 4.7 f tantalum or low esr ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. as a result, high input voltage applications in which a large power mosfet is being driven at high frequencies can
11 ltc3704 3704fb applicatio s i for atio wu uu cause the ltc3704 to exceed its maximum junction temperature rating. the junction temperature can be estimated using the following equations: i q(tot) i q + f ? q g p ic = v in ? (i q + f ? q g ) t j = t a + p ic ? r th(ja) the total quiescent current i q(tot) consists of the static supply current (i q ) and the current required to charge and discharge the gate of the power mosfet. the 10-pin msop package has a thermal resistance of r th(ja) = 120 c/w. as an example, consider a power supply with v in = 5v and v sw(max) = 12v. the switching frequency is 500khz, and the maximum ambient temperature is 70 c. the power mosfet chosen is the irf7805, which has a maximum r ds(on) of 11m (at room temperature) and a maximum total gate charge of 37nc (the temperature coefficient of the gate charge is low). i q(tot) = 600 a + 37nc ? 500khz = 19.1ma p ic = 5v ? 19.1ma = 95mw t j = 70 c + 120 c/w ? 95mw = 81.4 c this demonstrates how significant the gate charge current can be when compared to the static quiescent current in the ic. to prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high v in . a tradeoff between the operating frequency and the size of the power mosfet may need to be made in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their latest-and-great- est low q g , low r ds(on) devices. power mosfet manu- facturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. output voltage programming the output voltage is set by a resistor divider according to the following formula: vv r r ir o ref nfb =+ ? ? ? ? ? ? + ?? 1 2 1 2 where v ref = C1.230v, and i nfb is the current which flows out of the nfb pin (i nfb = C7.5 a). in order to properly dimension r2, including the effect of the nfb pin current, the following formula can be used: r vv v r i out ref ref nfb 2 1 = ? + ? ? ? ? ? ? the nominal 7.5 a current which flows out of the nfb pin has a production tolerance of approximately 2.5 a, so an output divider current of 500 a (r1 = 2.49k) results in a 0.5% uncertainty in the output voltage. for low power applications where the output voltage tolerance is less important, efficiency can be increased by increasing the value of r1. programming turn-on and turn-off thresholds with the run pin the ltc3704 contains an independent, micropower volt- age reference and comparator detection circuit that re- mains active even when the device is shut down, as shown in figure 8. this allows users to accurately program an input voltage at which the converter will turn on and off. the falling threshold voltage on the run pin is equal to the internal reference voltage of 1.248v. the comparator has 100mv of hysteresis to increase noise immunity. the turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: vv r r vv r r in off in on () () .? .? =+ ? ? ? ? ? ? =+ ? ? ? ? ? ? 1 248 1 2 1 1 348 1 2 1
12 ltc3704 3704fb applicatio s i for atio wu uu C + run comparator v in run r2 r1 input supply optional filter capacitor + C gnd 3704 f08a bias and start-up control 1.248v power reference 6v figure 8b. on/off control using external logic figure 8c. external pull-up resistor on run pin for ?lways on?operation figure 8a. programming the turn-on and turn-off thresholds using the run pin C + run comparator 1.248v 3704 f08b run 6v external logic control C + run comparator v in run r2 1m input supply + C gnd 1.248v 3704 f08c 6v the resistor r1 is typically chosen to be less than 1m. for applications where the run pin is only to be used as a logic input, the user should be aware of the 7v absolute maximum rating for this pin! the run pin can be connected to the input voltage through an external 1m resistor, as shown in figure 8c, for always on operation.
13 ltc3704 3704fb applications circuits a simple positive-to-negative application circuit for the ltc3704 is shown in figure 1. the basic operation of this circuit is shown in figure 9. during the on-time the inductor currents flow through the switch, and during the off-time these currents flow through the output diode. the use of inductors in series with both the input and output results in continuous currents in these capacitors, result- ing in low input and output noise. discontinuous currents flow in the switch, the coupling capacitor, and the diode. peak and average input and switch currents the control loop in the ltc3704 is measuring the peak switch current (either by using the r ds(on) of the power mosfet or by using a sense resistor in the mosfet source), so the output current needs to be reflected back to the switch in order to dimension the power mosfet and inductors properly. based on the fact that, ideally, the input power is equal to the output power, the maximum average input current is: ii d d in max o max max max () () C? C = 1 where i o(max) is a negative number. the peak input current is: ii d d in peak o max max max () () ?? C = ? + ? ? ? ? ? ? 1 21 in a positive-to-negative converter, however, the switch current is equal to i in + i o , so the maximum average switch current is: ii d sw max o max max () () ? = ? ? 1 1 and the peak switch current is: ii d sw peak o max max () () ?? C = ? + ? ? ? ? ? ? 1 2 1 1 the maximum duty cycle, d max , should be calculated at minimum v in . ripple current i l and the ?factor the constant in the equation above represents the percentage peak-to-peak total ripple current in the induc- tor, relative to its maximum value. for example, if 30% ripple current is chosen, then = 0.30, and the peak current is 15% greater than the average. for a current mode converter operating in ccm, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. for the ltc3704, this ramp compensation is internal. having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. if too large an inductor is used, the resulting current ramp ( i l ) will be small relative to the applicatio s i for atio wu uu figure 9. positive-to-negative converter operation duty cycle considerations for the positive-to-negative converter shown in figure 1, the duty cycle of the main switch in ccm is: d v vv o oin = C where v o is a negative number. the maximum output voltage for this converter (in ccm) is: vv d d o max in min max max () () ? C = 1 the maximum duty cycle capability of the ltc3704 is typically 92%. + +C + on r l v out v in l1 l2 a) current flow during the switch on-time + +C + off r l v out v in l1 l2 b) current flow during the switch off-time 3704 f09
14 ltc3704 3704fb internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). if too small an inductor is used, but the converter is still operating in ccm (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. to ensure good current mode gain and avoid subharmonic oscillation, it is recom- mended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average switch current. for example, if the maximum average switch current is 1a, choose a i l between 0.2a and 0.4a, and a value between 0.2 and 0.4. inductor selection selecting inductors for a positive-to-negative converter is slightly more complicated than for a single-inductor topol- ogy like a buck or boost. the use of separate, uncoupled inductors can reduce the size of the solution, at the expense of input and output ripple. using a coupled inductor complicates the design procedure, but can result in significantly lower input and/or output ripple. it will also reduce the number of components that the purchasing department has to keep track of. regardless of the design goals, however, the inductor selection process is an iterative one. the best recommen- dation is to use the equations as a guideline, and then to build a solution and measure the circuits performance. if the measured performance deviates from the design guide- lines, substitute a bigger (or smaller) inductor, as appro- priate, and repeat the measurements. in addition, do your best to minimize layout parasitics, which can have a significant effect on circuit performance. the inductor currents for a positive-to-negative converter are calculated at full load current and minimum input voltage. the peak inductor currents can be significantly higher than the output current, especially with smaller inductors and lighter loads. the following formulae as- sume uncoupled inductors and ccm operation. ii d d ii l peak o max max max l peak o max 1 2 1 21 1 2 () () () () ?? C ? = ? + ? ? ? ? ? ? = ? + ? ? ? ? ? ? where represents the percentage of ripple current. in a positive-to-negative converter, however, the switch cur- rent is the sum of the two inductor currents. therefore, ii d sw peak o max max () () C?? C =+ ? ? ? ? ? ? 1 2 1 1 since the control loop is looking at the switch current, and since the internal slope compensation is acting on this switch current, the ripple current percentage should be between 20% and 40% of the maximum average current at v in(min) and i o(max) . this corresponds to a value of in the equations above between 0.20 and 0.40. expressing this ripple current as a function of the output current results in the following equation for calculating the induc- tor value: ll v if d in min sw max 12 == () ? ? where: ii d sw o max max = C? ? C () 1 1 by using a coupled inductor with a 1:1 turns ratio, the value of inductance in the equation above can be replaced by 2l due to mutual inductance. doing this maintains the same total ripple current and energy storage in the inductor. substituting 2l yields the following equation for 1:1 coupled inductors: ll v if d in min l max 12 2 == () ?? ? applicatio s i for atio wu uu
15 ltc3704 3704fb the initial equations for i l1(peak) and i l2(peak) . if a coupled inductor is used, make sure that the minimum saturation current for the parallel configuration exceeds the maxi- mum switch current, or: ii d lsat min o max max () ( ) C?? C + ? ? ? ? ? ? 1 2 1 1 the saturation current rating should be checked at mini- mum input voltage (which results in the highest average inductor current) and maximum load current. operating in discontinuous mode discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in figure 10. once the inductor current is near zero, the switch and diode capacitances resonate with the induc- tance to form damped ringing at 1mhz to 10mhz. if the off-time is long enough, the drain voltage will settle to the input voltage. depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power mosfet to go below ground where it is clamped by the body diode. this ringing is not harmful to the ic and it has not been shown to contribute significantly to emi. any attempt to damp it with a snubber will degrade the efficiency. power mosfet or sense resistor selection if the maximum voltage on the drain of the power mosfet (which is v in(max) + v out , plus any transients) is less than 36v then the circuit can take advantage of the ltc3704s no r sense technology in order to improve efficiency and eliminate the sense resistor. for higher switch voltages the sense pin should be connected to a resistor in the source of the power mosfet, as shown in figure 2. internal leading-edge blanking is provided in the ltc3704 to eliminate the need for filtering components on the sense pin. in both positive-to-negative and flyback converters the maximum switch current is equal to the input current plus the output current. as a result, the peak switch current is: ii d sw peak o max max () () C?? C =+ ? ? ? ? ? ? 1 2 1 1 where i o(max) is a negative number. during the switch on-time, the control circuit limits the maximum voltage drop across the power mosfet to 150mv (at low duty cycles). the peak switch current is therefore limited to 150mv/r ds(on) . the relationship be- tween the maximum load current, the duty cycle and the r ds(on) of the power mosfet is: r v i ds on sense max sw peak () () () ? + ? ? ? ? ? ? 1 1 2 again, where i o(max) is a negative number. the v sense(max) term is typically 150mv at low duty cycle, and is reduced to about 100mv at a duty cycle of 92% due to slope compensation, as shown in figure 11. the term ac- counts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/ c. figure 12 illustrates the variation of r ds(on) over temperature for a typical power mosfet (normalized for simplicity). or figure 10. discontinuous mode waveforms (mode/sync = intv cc , pulse-skip mode) for the circuit in figure 1. applicatio s i for atio wu uu v in = 15v no load v ds 10v/div i l1 1a/div 1 s/div 3704 f10
16 ltc3704 3704fb another method of choosing which power mosfet to use is to check the maximum output current for a given r ds(on) , since mosfet on-resistances are generally available in discrete values. iv d r o max sense max max ds on () () () C? C ?? = + ? ? ? ? ? ? 1 1 2 for the case where a conventional sense resistor is used, rv d i sense sense max max o max = + ? ? ? ? ? ? () () ? C ? 1 1 2 sense resistors are generally low tc and are available with different ranges of tolerance depending on price. the power dissipated in the sense resistor is: pi rd sense sw peak sense max = () ?? 2 calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the con troller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and tempera- ture), and for the worst-case specifications for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a positive-to- negative converter is: p i d rd kv v i d cf fet omax max ds on max t in o omax max rss = ? ? ? ? ? ? + C C ??? ?( C ) ? C ?? () () . () 1 1 2 185 where i o(max) and v o are negative numbers. the first term in the equation above represents the i 2 r losses in the device, and the second term, the switch- ing losses. the constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) figure 12. normalized r ds(on) vs temperature figure 11. maximum sense threshold voltage vs duty cycle applicatio s i for atio wu uu duty cycle 0 maximum current sense voltage (mv) 100 150 0.8 3704 f11 50 0 0.2 0.4 0.5 1.0 200 junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 3704 f12 0.5 0 0 50 100 2.0
17 ltc3704 3704fb the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. the output diode in a positive-to-negative converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to v in(max) C v o . the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. ii d d peak o max max () () C? C =+ ? ? ? ? ? ? 1 2 1 1 the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dissipation. selecting the dc coupling capacitor the voltage on the coupling capacitor in a positive-to- negative converter is v in(max) C v o , plus any additional v due to the ripple currents in the inductors. generally, the dc coupling capacitor is dimensioned based on the high rms ripple which flows in it, as shown in figure 13. the minimum rms current rating of this capacitor must exceed: ii d d rms cap o max max max () ( ) C? C = 1 a low esr and esl, x5r- or x7r-type ceramic capacitor is recommended here. selecting the output capacitor the output ripple voltage appears as a triangular wave- form riding on v o , due to the ripple current of l2 (the dc component of the current in l2 equals the output current). this ripple current flows through the esr and bulk capaci- tance of the output capacitor to produce the overall ripple voltage on this node. using the off-time to calculate this ripple current results in the following equation for i l2 : i d f v l l max o 2 1 2 = C C ? where v o is a negative number. the output ripple voltage is therefore: v d f v l esr fc op p max o o (C) C ? CC ?? = ? ? ? ? ? ? 1 2 1 8 the esr can be minimized by using high quality, x5r- or x7r-dielectric ceramic capacitor in parallel with a larger value tantalum or aluminum electrolytic bulk capacitor. depending upon the application, it may be that the ceramic capacitor alone will be sufficient. the rms ripple current rating of the output capacitor needs to be greater than: applicatio s i for atio wu uu figure 13. ripple current in the dc coupling capacitor 1a/div 500ns/div 3704 f13
18 ltc3704 3704fb i d f v l rms cout max o () ? (C ) ? 1 12 1 2 it should be noted that these equations assume no cou- pling between the inductors. if the inductors are wound on the same core, the ripple currents at the input and output can be tuned to very low values, and so the equations above would be extremely conservative. it is highly rec- ommended that the user experiment in the lab with the same magnetics and capacitors which will be used in production. note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest product of esr and size of any aluminum electrolytic, at a somewhat higher price. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. applicatio s i for atio wu uu table 1. recommended component manufacturers vendor components telephone web address avx capacitors (207) 282-5111 avxcorp.com bh electronics inductors, transformers (952) 894-9590 bhelectronics.com coilcraft inductors (847) 639-6400 coilcraft.com coiltronics inductors (407) 241-7876 coiltronics.com diodes, inc diodes (805) 446-4800 diodes.com fairchild mosfets (408) 822-2126 fairchildsemi.com general semiconductor diodes (516) 847-3000 generalsemiconductor.com international rectifier mosfets, diodes (310) 322-3331 irf.com irc sense resistors (361) 992-7900 irctt.com kemet tantalum capacitors (408) 986-0424 kemet.com magnetics inc toroid cores (800) 245-3984 mag-inc.com microsemi diodes (617) 926-0404 microsemi.com murata-erie inductors, capacitors (770) 436-1300 murata.co.jp nichicon capacitors (847) 843-7500 nichicon.com on semiconductor diodes (602) 244-6600 onsemi.com panasonic capacitors (714) 373-7334 panasonic.com sanyo capacitors (619) 661-6835 sanyo.co.jp sumida inductors (847) 956-0667 sumida.com taiyo yuden capacitors (408) 573-4150 t-yuden.com tdk capacitors, inductors (562) 596-1212 component.tdk.com thermalloy heat sinks (972) 243-4321 aavidthermalloy.com tokin capacitors (408) 432-8020 tokin.com toko inductors (847) 699-3430 tokoam.com united chemicon capacitors (847) 696-2000 chemi-com.com vishay/dale resistors (605) 665-9301 vishay.com vishay/siliconix mosfets (800) 554-5565 vishay.com vishay/sprague capacitors (207) 324-4140 vishay.com zetex small-signal discretes (631) 543-7100 zetex.com
19 ltc3704 3704fb aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. an excellent choice is avx tps series of surface mount tantalum. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. input capacitor selection the input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10 f to 100 f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a positive-to- negative converter is: i v lf d rms cin in min max () () ? ? ? = 1 12 1 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! burst mode operation and considerations the choice of mosfet r ds(on) and inductor value also determines the load current at which the ltc3704 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i mv r burst peak ds on () () = 30 which represents about 20% of the maximum 150mv sense pin voltage. the corresponding average current depends upon the amount of ripple current. lower induc- tor values (higher i l ) will reduce the load current at which burst mode operations begins, since it is the peak current that is being clamped. the output voltage ripple can increase during burst mode operation if i l is substantially less than i burst . this can occur if the input voltage is very low or if a very large inductor is chosen. at high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. however, because i l is small, it takes multiple cycles for the current to ramp back up to i burst(peak) . during this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. generally, it is a good idea to choose a value of inductor i l between 20% and 40% of i in(max) . the alternative is to either increase the value of the output capacitor or disable burst mode operation using the mode/sync pin. burst mode operation can be defeated by connecting the mode/sync pin to a high logic-level voltage (either with a control input or by connecting this pin to intv cc ). in this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduc- tion mode (ccm) at full load, down into deep discontinu- ous conduction mode (dcm) at light load. prior to skip- ping pulses at very light load (i.e., < 5-10% of full load), the controller will operate with a minimum switch on-time in dcm. pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. checking transient response the regulator loop response can be verified by looking at the load transient response. switching regulators gener- ally take several cycles to respond to an instantaneous step in resistive load current. when the load step occurs, v o immediately shifts by an amount equal to ( i load )(esr), and then c o begins to charge or discharge (depending on the direction of the load step) as shown in figure 14. the figure 14. load step response for the circuit in figure 1. applicatio s i for atio wu uu v in = 5v v out = C5v v out (ac) 100mv/div i out (dc) 1a/div 250 s/div 3704 f14 2a 0.5a
20 ltc3704 3704fb applicatio s i for atio wu uu regulator feedback loop acts on the resulting error amp output signal to return v o to its steady-state value. during this recovery time, v o can be monitored for overshoot or ringing that would indicate a stability problem. a second, more severe transient can occur when connect- ing loads with large (> 1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c o , causing a nearly instantaneous drop in v o . no regulator can deliver enough current to prevent this prob- lem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. design example: a 5v to 15v input, ?v at 2a output positive-to-negative converter the design example presented here will be for the circuit shown in figure 1. the input voltage range is 5v to 15v, and the output is -5v. the maximum load current is 2a at an input voltage of 5v (3a peak), and 3a at an input voltage of 15v (5a peak). 1. the maximum duty cycle of the main switch is: d v vv max out out in min = ? == () C C % 5 10 50 2. pulse-skip operation is chosen, so the mode/sync pin is connected to the intv cc pin. 3. the operating frequency is chosen to be 300khz to reduce the size of the inductors. from figure 5, the resistor from the freq pin to ground is 80.6k. 4. a total inductor ripple current of 40% of the maximum is chosen, so the inductor ripple current is: = ? == ii d d ia lomax max max l 1 1 1 04 20 05 105 08 ?? C .?.? . C. . () for a standard 1:1 coupled inductor, the inductance is therefore: ll v if d k h in min l max 12 2 5 208300 05 52 1 == == () ?? ? ?.? ?. . the minimum saturation current for this inductor is: ii d a lsat min o max max () ( ) C?? C .?.? C. . + ? ? ? ? ? ? == 1 2 1 1 12 20 1 105 48 the inductor chosen is a bh electronics part # 510-1009, which has an open circuit parallel inductance of 4.56 h and a maximum dc current rating of 6.5a. 5. for the power mosfet, rv d i ds on sense max max omax () ( ) () ? C ?? + ? ? ? ? ? ? 1 1 2 at the maximum duty cycle of 50%, the maximum sense pin voltage is reduced to 130mv due to slope compensa- tion, as shown in figure 11. assuming a maximum junction temperature of 125 c for the power mosfet, = 1.5, and rm ds on () .? .C C. ? . ?. . = 0 130 05 1 12 20 15 18 1 the mosfet chosen was siliconix/vishays si4884, which has a maximum r ds(on) = 16.5m at v gs = 4.5v at 25 c. the minimum bv dss = 30v and the maximum gate charge is q g = 20nc. 6. the output diode must withstand a reverse voltage of v in(max) C v o = 20v and a continuous current of i o(max) = 5.0a (peak output current at v in = 15v). the peak current in the diode is: iia d peak o max () () ? =+ ? ? ? ? ? ? = 1 2 6 the power dissipated in this diode at full load is:
21 ltc3704 3704fb applicatio s i for atio wu uu p d = i o(max) ? v f assuming a maximum junction temperature of 125 c and a forward voltage of approximately 0.33v at 3a (the maximum output current at v in = 15v), this diode will dissipate 1w at full load. the diode selected was the mbrd835l from on semiconductor, packaged in a d-pak. 7. the dc coupling capacitor must be capable of handling an rms current of: ii d d a d peak o max max max () () C? C == 1 3 figure 15. 5v to 15v input, ?v output at 2a-3a(5a peak) positive-to-negative converter with soft-start and undervoltage lockout. figure 16. efficiency vs output current figure 17. maximum output current vs input voltage run i th nfb freq mode/sync sense v in intv cc gate gnd ltc3704 r t 80.6k 1% r1 154k 1% c vcc 4.7 f x5r m1 c in : tdk c5750x5r1c476m c dc : tdk c5750x7r1c476m c out : tdk c5750x5r0j107m c vcc : taiyo yuden lmk316bj475ml d1 ? l1* l2* c out 100 f x5r (x2) v in 5v to 15v v out C5.0v 2a to 3a (5a peak) gnd d1: on semiconductor mbrd835l d2: cdmsh-3 l1, l2: bh electronics bh510-1009 m1: siliconics/vishay si4884 q1: mmbt3904 r c 3k c c1 4.7nf c in 47 f x5r 1 2 3 4 5 6 7 8 10 9 c dc 47 f x5r 3704 f15 r2 68.1k 1% c1 1nf r fb1 1.21k 1% r fb2 3.65k 1% q1 d2 r ss2 100 c ss 10nf r ss1 750 ? output current (a) 0.001 efficiency (%) 0.1 10 100 90 80 70 60 50 40 30 20 3704 f16 0.01 1 v in = 5v v in = 15v v in = 10v fet = si4884 l = bh510-1009 v o = C5v freq = 300khz input voltage (v) 510 i o(max) (a) 6 5 4 3 2 1 0 3704 f17 15
22 ltc3704 3704fb v k k mv op p () C. ? . . C. C ?? . ? = ? ? ? ? ? ? = 105 300 50 35 0 0016 1 8 300 100 13 7 this ripple voltage calculation also assumes no coupling between the inductors, making the 13.7mv number very conservative. figure 15 illustrates the same basic application shown in figure 1, with the added features of soft-start and undervoltage lockout on the input supply. figures 16 through 21 illustrate the measured performance for this converter. the peak efficiency is 87% at a load current of 2a and the peak-to-peak output ripple is less than 10mv. figures 19 and 20 illustrate the load step response at 5v and 15v input, and figure 21, the start-up characteristics with a resistive load. applicatio s i for atio wu uu the capacitor used was a tdk 47 f, 16v x5r-dielectric ceramic (c5750x5r1c476m), mainly because of its low esr (2.4m ) and high rms current capability. 8. the peak-to-peak output ripple is: v d f v l esr fc op p max o o () C ? CC ?? ? = ? ? ? ? ? ? 1 2 1 8 as a first try, a tdk 100 f, 6.3v x5r-dielectric ceramic capacitor was chosen (c5750x5r0j107m). this capaci- tor has a very low 1.6m of esr. as a result, the peak-to- peak output ripple voltage is: figure 18. output ripple voltage and inductor current for the circuit in figure 15 figure 21. soft-start for the circuit in figure 15 figure 20. load step response at v in = 15v for the circuit in figure 15 figure 19. load step response at v in = 5v for the circuit in figure 15 v in = 5v i out = C2v v out (ac) 10mv/div i l2 (dc) 1a/div 1 s/div 3704 f18 v in = 5v v out (ac) 100mv/div i out (dc) 1a/div 250 s/div 3704 f19 2a 0.5a v in = 15v v out (ac) 100mv/div i out (dc) 1a/div 250 s/div 3704 f20 2a 0.5a v in = 5v v out 1v/div i out 1a/div 1ms/div 3704 f21 v out i out
23 ltc3704 3704fb applicatio s i for atio wu uu pc board layout checklist 1. in order to minimize switching noise and improve output load regulation, the gnd pin of the ltc3704 should be connected directly to 1) the negative termi- nal of the intv cc decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the source of the power mosfet or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to pin 6. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resistance and induc- tance. ltc3704 m1 v in 3704 f?? v out l1 r t r c c c1 r3 c in c out c vcc r1 r2 pseudo-kelvin signal ground connection true remote output sensing vias to ground plane r4 pin 1 c out d1 l2 c dc c3 c c2 1 2 3 4 5 6 12 11 10 9 8 7 figure 22. ltc3704 positive-to-negative converter suggested layout run i th nfb freq mode/ sync sense v in intv cc gate gnd ltc3704 r4 10 9 8 7 6 1 2 3 4 5 c vcc pseudo-kelvin ground connection c in m1 d1 l1 v in gnd 3704 f23 c out r c r1 r t bold lines indicate high current paths r2 c c1 r3 + c3 l2 c dc v out c c2 figure 23. ltc3704 positive-to-negative converter layout diagram
24 ltc3704 3704fb applicatio s i for atio wu uu 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground plane is to be used for high dc currents, choose a path away from the small-signal components. 3. place the c vcc capacitor immediately adjacent to the intv cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. a low esr x5r-dielectric 4.7 f ceramic capacitor works well here. 4. the high di/dt loop from the drain of the power mosfet, through the coupling capacitor and back through the diode to ground should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase hf noise on the drain node. it is also important to keep the cathode of the diode as close as possible to the mosfet source or the bottom of the sense resistor. 5. check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing which can exceed the maximum speci- fied voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power mosfet. not all mosfets are created equal (some are more equal than others). 6. place the small-signal components away from high frequency switching nodes. in the layout shown in figure 22, all of the small-signal components have been placed on one side of the ic and all of the power components have been placed on the other. this also allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the ic ground pin in one direction (to the bottom plate of the intv cc decoupling capacitor) and small-signal currents flow in the other direction. 7. if a sense resistor is used in the source of the power mosfet, minimize the capacitance between the sense pin trace and any high frequency switching nodes. the ltc3704 contains an internal leading edge blanking time of approximately 180ns, which should be ad- equate for most applications. 8. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the ltc3704 in order to keep the high impedance fb node short. 9. for applications with multiple switching power con- verters connected to the same input supply, make sure that the input filter capacitor for the ltc3704 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the ltc3704. a few inches of pc trace or wire (l 100nh) between the c in of the ltc3704 and the actual source v in should be sufficient to prevent current sharing problems.
25 ltc3704 3704fb applicatio s i for atio wu uu run i th nfb freq mode/sync sense v in intv cc gate gnd ltc3704 r t 80.6k 1% c vcc 4.7 f x5r m1 d1 ? l1* l2* c out 100 f x5r v in 3v to 5v v out C8.0v 1.2a to 2.5a gnd d1: diodes inc b320b l1, l2: bh electronics bh 510-1009 m1: siliconix si9426 r c 14.7k c c1 4.7nf c in 47 f x5r 1 2 3 4 5 6 7 8 10 9 c dc 22 f x5r ? r fb1 2.49k 1% r fb2 13.7k 1% 3704 f24 input voltage (v) 5.0 3704 f25 3.5 4.0 4.5 3.0 i o(max) (a) 2 3 1 0 output current (a) 0.001 efficiency (%) 0.1 10 100 95 90 85 80 75 70 65 60 55 50 3704 f26 0.01 1 v in = 5v v in = 3v figure 24. 3v to 5v input, ?v at 1.2a output converter figure 26. output efficiency at 3v and 5v input figure 25. maximum output current vs input voltage figure 28.load step response at 5v input figure 27. load step response at 3v input v in = 3v v out (ac) 100mv/div i out (dc) 0.5a/div 250 s/div 3704 f27 1.2a 0.6a v in = 3v v out (ac) 100mv/div i out (dc) 0.5a/div 250 s/div 3704 f27 1.2a 0.6a
26 ltc3704 3704fb + run i th nfb freq mode/sync sense v in intv cc gate gnd ltc3704 r t 120k f = 200khz * vp5-0155 (primary = 3 windings in parallel) c1 4.7 f 10v x5r + c in 220 f 16v tps c3 10 f 25v x5r irl2910 r s 0.012 d3 10bq060 5 ? ? v in 7v to 12v t1* 1, 2, 3 r c 82k c c1 1nf c c2 100pf c r 1nf r1 49.9k 1% r2 150k 1% d4 10bq060 6 ? d2 10bq060 4 ? + c4 10 f 25v x5r + c out 3.3 f 100v gnd v out1 C24v 200ma v out2 C72v 200ma + c5 10 f 25v x5r + c2 4.7 f 50v x5r r fb1 2.49k 1% r fb2 45.3k 1% uv + = 5.4v uv C = 5.0v 3704 f29 figure 29. high power slic supply applicatio s i for atio wu uu
27 ltc3704 3704fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661)
28 ltc3704 3704fb ? linear technology corporation 2006 lt 0307 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt ? 1175 negative linear low dropout regulator user-selectable current limit from 200ma to 800ma, 0.4v dropout at 500ma, 45 a operating current lt1619 current mode pwm controller 300khz fixed frequency, boost, sepic, flyback topology ltc1624 current mode dc/dc controller so-8; 200khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1700 no r sense synchronous step-up controller up to 95% efficiency, operation as low as 0.9v input ltc1871 no r sense boost, flyback and sepic controller 2.5v v in 30v, current mode control, programmable f osc from 50khz to 1mhz ltc1872 sot-23 boost controller delivers up to 5a, 550khz fixed frequency, current mode lt1930 1.2mhz, sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1931 inverting 1.2mhz, sot-23 converter positive-to-negative dc/dc conversion, miniature design lt1964 thinsot tm linear low dropout regulator 200ma output current, low noise, 340mv drop out at 200ma, 5-lead thinsot ltc3401/ltc3402 1a/2a 3mhz synchronous boost converters up to 97% efficiency, very small solution, 0.5v v in 5v thinsot is a trademark of linear technology corporation. high efficiency positive-to-negative converter r t 80.6k 1% r1 1.21k 1% r2 3.65k 1% r4 154k 1% c vcc 4.7 f m1 c in : tdk c5570x5r1c476m c out1 : tdk c5750x5r0j107m c out2 : panasonic eefue0j151r c dc : tdk c5750x7r1e226m c vcc : tdk c2012x5r0j475k d1 l1* c in 47 f 16v l2* r c 9.1k c c1 10nf c c2 330pf c out1 100 f 6.3v v in 5v to 15v v out C5v 5a gnd 3704 ta02 + c out2 150 f 6.3v d1: fairchild mbr2035ct l1, l2: coiltronics vp5-0053 (*coupled inductors, with 3 windings in parallel on primary and secondary) m1: international rectifier irf7822 c dc 22 f 25v x7r r5 68.1k 1% c9 1nf optional run i th nfb freq mode/sync sense v in intv cc gate gnd ltc3704 u typical applicatio

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